Multi-level Sequential Circuit Partitioning for Delay Minimization of VLSI Circuits

Abstract

Sequential graph partitioning algorithms have been developed to fulfill the requirements of emerging multi-phase problems in circuit delay models. In this paper we propose a heuristic algorithm for k- partition, which minimizes the circuit delay and cut size. Experimental results with MCNC benchmark circuits have shown that the delay in the circuit can be reduced by marginally in comparison with the other algorithms [2,3,11].