Year: 2012
International Journal of Numerical Analysis and Modeling, Vol. 9 (2012), Iss. 2 : pp. 208–216
Abstract
Solving a super-high dimensional equations group is widely used in science and engineering, but the slow solution speed is the biggest problem researchers face. Research on FPGA based evolvable hardware chips for solving the super-high dimensional equations group (SHDESC) is proposed in this paper. These chips can be implemented on a million-gate scale FPGA chip. The core architecture of SHDESC is a systolic array which consists of thousands of special arithmetic units and can execute many super-high dimensional matrix operations parallelly in short time as well as really achieve the purpose of high speed solution in hardware/software codesign. The experiments show that these chips can achieve high precision results in a short period of time to solve a super-high dimensional equations group.
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Journal Article Details
Publisher Name: Global Science Press
Language: English
DOI: https://doi.org/2012-IJNAM-621
International Journal of Numerical Analysis and Modeling, Vol. 9 (2012), Iss. 2 : pp. 208–216
Published online: 2012-01
AMS Subject Headings: Global Science Press
Copyright: COPYRIGHT: © Global Science Press
Pages: 9
Keywords: Evolvable Hardware Super-High Dimensional Equations Group FPGA Hardware/Software Codesign Systolic Array.