Multi-level Sequential Circuit Partitioning for Delay Minimization of VLSI Circuits
Year: 2007
Journal of Information and Computing Science, Vol. 2 (2007), Iss. 1 : pp. 66–70
Abstract
Sequential graph partitioning algorithms have been developed to fulfill the requirements of emerging multi-phase problems in circuit delay models. In this paper we propose a heuristic algorithm for k- partition, which minimizes the circuit delay and cut size. Experimental results with MCNC benchmark circuits have shown that the delay in the circuit can be reduced by marginally in comparison with the other algorithms [2,3,11].
Journal Article Details
Publisher Name: Global Science Press
Language: English
DOI: https://doi.org/2024-JICS-22822
Journal of Information and Computing Science, Vol. 2 (2007), Iss. 1 : pp. 66–70
Published online: 2007-01
AMS Subject Headings:
Copyright: COPYRIGHT: © Global Science Press
Pages: 5